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NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I 2 C-bus LED controller
8. Characteristics of the I 2 C-bus
The I 2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 16 ).
SDA
SCL
data line
stable;
change
of data
data valid
allowed
mba607
Fig 16. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 17 ).
SDA
SCL
S
START condition
P
STOP condition
mba608
Fig 17. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter ’; a device receiving is the ‘receiver ’. The
device that controls the message is the ‘master ’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 18 ).
PCA9685
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 September 2010
? NXP B.V. 2010. All rights reserved.
29 of 51
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